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DM505LRBABF 데이터시트(PDF) 93 Page - Texas Instruments

부품명 DM505LRBABF
상세설명  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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DM505LRBABF 데이터시트(HTML) 93 Page - Texas Instruments

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DM505
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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
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Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
31
80
µA
CI
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA sink current
0.4
V
IOLmin
Low-level output current @VOL=0.4V
3
mA
IOLmin
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)
6
mA
tOF
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10
pF to 200 pF (Proper External Resistor Value should be used as per I2C
spec)
20+0.1×C
b
250
ns
Output fall time from VIHmin to VILmax with a bus capacitance CB from 300
pF to 400 pF (Proper External Resistor Value should be used as per I2C
spec)
40
290
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see Table 4-1, POWER [10] column.
(2) For more information on the I/O cell configurations, see the Control Module section of the Device TRM.
Table 5-8. IQ1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk;
Balls ABF: J2;
1.8-V Mode
VIH
Input high-level threshold
0.75 ×
VDDS
V
VIL
Input low-level threshold
0.25 ×
VDDS
V
VHYS
Input hysteresis voltage
100
mV
IIN
Input current at each I/O pin
2
11
µA
CPAD
Pad capacitance (including package capacitance)
1
pF
3.3-V Mode
VIH
Input high-level threshold
2.0
V
VIL
Input low-level threshold
0.6
V
VHYS
Input hysteresis voltage
400
mV
IIN
Input current at each I/O pin
5
11
µA
CPAD
Pad capacitance (including package capacitance)
1
pF
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv1). For more information on the power supply name and the
corresponding ball, see Table 4-1, POWER [10] column.
Table 5-9. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: porz;
Balls ABF: G3;
1.8-V Mode
VIH
Input high-level threshold
1.2
V
VIL
Input low-level threshold
0.4
V
VHYS
Input hysteresis voltage
40
mV
IIN
Input current at each I/O pin
0.02
1
µA



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