TDA2SA datasheet(12/427 Pages) TI2

12 / 427 page

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Terminal Configuration and Functions

NOTE

For programmable buffer strength:

–

The default value is given in Table 4-2.

–

A note describes all possible values according to the selected muxmode.

14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.

Pullup and pulldown resistors can be enabled or disabled via software.

–

PU: Internal pullup

–

PD: Internal pulldown

–

PU/PD: Internal pullup and pulldown

–

PUx/PDy: Programmable internal pullup and pulldown

–

PDy: Programmable internal pulldown

–

An empty box means No pull

15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or

logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.

–

0: Logic 0 driven on the peripheral's input signal port.

–

1: Logic 1 driven on the peripheral's input signal port.

–

blank: Pin state driven on the peripheral's input signal port.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected

results. This can be easily prevented with the proper software configuration (Hi-Z mode is not

an input signal).

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that

pad’s behavior is undefined. This should be avoided.

CAUTION

Peripherals

exposed

Ball

Characteristics

Table

and

Multiplexing

Characteristics Table represent functionality of a superset device. Not all

exposed peripherals are supported on ADAS devices. For peripherals

supported on ADAS family of products please refer to Table 3-1, Device

Comparison.

NOTE

Some of the DDR1 and DDR2 signals have an additional state change at the release of porz.

The state that the signals change to at the release of porz is as follows:

drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen,

ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn, ddr2_wen,

ddr2_ba[2:0], ddr2_a[15:0].

OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0],

ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0],

ddr2_d[31:0].

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