MP5026

– 16V, 20A, 2.8mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION

MP5026 Rev. 1.0

MonolithicPower.com

15

7/5/2023

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2023 MPS. All Rights Reserved.

OPERATION

The MP5026 is designed to limit the inrush

current to the load when a circuit card is

inserted into a live backplane power source.

This limits the backplane voltage drop and the

dV/dt of the voltage to the load. The device

provides an integrated solution for monitoring

the input voltage (VIN), output voltage (VOUT),

output current (IOUT), and die temperature to

eliminate the need for an external current-sense

power

resistor,

power

MOSFET,

and

temperature-sense device.

The maximum load at the output is current-

limited via sense MOSFET topology. The

current limit is controlled by a low-power

resistor connected between the ISET pin and

ground.

The

MP5026

provides

a

variety

of

fault

protections, including over-current protection

(OCP), short-circuit protection (SCP), over-

temperature

protection

(OTP),

damaged

MOSFET

detection,

over-voltage

protection

(OVP), and under-voltage protection (UVP).

Start-Up Sequence

For hot-swap applications, the MP502

6’s input

can experience a voltage spike or transient

during the hot-plug process. This is caused by

the parasitic inductance of the input trace and

the input capacitor. To help stabilize VIN, an

insertion delay is implemented before the main

MOSFET turns on (see Figure 2).

TIMER

t

tIDT

VIN

1.21V

VGS

VOUT

40µA

SS

3.3V Clamp

3.3V

PG

VCC

UVLO

24µA Gate Charge

Insertion Delay Time

Figure 2: Start-Up Sequence

After VIN and the VCC voltage (VCC) exceed

their respective under-voltage lockout (UVLO)

thresholds, the TIMER pin charges the external

timer capacitor (CTMR) (nF) via a 4µA constant-

current source.

The insertion delay time (tIDT) is the time period

during which CTMR is charged from 0V to 1.21V

via the internal 4µA current source. To set tIDT,

select a sufficient capacitance from TIMER to

ground. tIDT can be determined with Equation

(1):

=

IDT

TMR

1.21

t

(ms)

C

(nF)

4

(1)

For example, a 10nF capacitor requires a 3ms

tIDT.

Once tIDT finishes and the EN/UV pin exceeds

1.4V, the MOSFET is charged via the internal

24

μA charge pump. If the gate-to-source (GS)

voltage (VGS) exceeds its threshold (VGS_TH), the

MOSFET turns on and VOUT rises.

Soft Start (SS)

A soft-start capacitor (CSS) determines the soft-

start time (tSS). If EN/UV is pulled high and tIDT

finishes, a constant-current source proportional

to VIN charges the soft-start voltage (VSS). This

enables a constant tSS independent of VIN. VOUT

rises at a similar slew rate to VSS.

CSS can be calculated with Equation (2):

SS

SS

SS

t (ms)

C (nF) = 9

R (M

Ω)



(2)

Where the soft-start resistance (RSS) is 0.89MΩ.

For example, a 100nF capacitor sets tSS to

9.9ms. If the load capacitance is extremely

large, then the current required to maintain the

preset tSS should exceed the start-up current

limit. Then the rise time is controlled by the load

capacitor (CLOAD) and the start-up current limit.

Float the SS pin to generate a fast ramp-up

voltage. A 24

μA current source pulls up the

power MOSFET gate. The gate charge current

controls the VOUT rise time, and tSS is about 1ms,

which is the minimum VOUT tSS.