LLCC68 datasheet(24/111 Pages) SEMTECH

24 / 111 page

LLCC68

Data Sheet

Rev. 1.1

DS.LLCC68.W.APP

Dec 2024

24 of 111

Semtech

LLCC68

www.semtech.com

4.1.4 TCXO Control Block

Under certain circumstances, typically small form factor designs with reduced heat dissipation or environments with extreme temperature

variation, it may be required to use a TCXO (Temperature Compensated Crystal Oscillator) to achieve better frequency accuracy. This

depends on the complete system, transmitter and receiver. The specification FERR_L in Section Table 3-8: "Receive Mode Specifications"

on page 19 provides information on the maximum tolerated frequency offset for optimal receiver performance.

Figure 4-2: TCXO Control Block

When a TCXO is used, it should be connected to pin 3 XTA, through a 220 resistor and a10pF DC-cut capacitor. Pin 4 XTB should be left not

connected. Pin 6 DIO3 can be used to provide a regulated DC voltage to power the TCXO, programmable from 1.6 to 3.3V. VBAT should

always be 200mV higher than the programmed voltage to ensure proper operation. AN1200.59 provides guidelines for the selection of

32MHz TCXOs and associated components.

The nominal current drain is 1.5mA, but the regulator can support up to 4mA of load. A clipped-sine-wave output TCXO is required, with the

output amplitude not exceeding 1.2V peak-to-peak. The commands to enable TCXO mode are described in Section 13.3.6

"SetDIO3AsTCXOCtrl" on page 81 , and that includes DC voltage and timing information.

Note: A complete Reset of the chip as described in Section 8.1 "Reset" on page 48 is required to get back to normal XOSC operation,

after the chip has been set to TCXO mode with the command SetDIO3AsTCXOCtrl.

4.2 Phase-Locked Loop (PLL)

A fractional-N third order sigma-delta PLL acts as the frequency synthesizer for the LO of both receiver and transmitter chains. The LLCC68

can cover continuously all the sub-GHz frequency range 150-960MHz. The PLL is capable of auto-calibration and has low switching-on or

hopping times. Frequency modulation is performed inside the PLL bandwidth. The PLL frequency is derived from the crystal oscillator circuit

which uses an external 32MHz crystal reference.

TCXO

SX1261/SX1262

XTA

XTB (leave open)

DIO3

10 pF

Programmable DC

voltage 1.6 to 3.3 V

1.5 to 4

100 nF

220

LLCC68

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