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ADE7166ASTZF16 데이터시트(PDF) 66 Page - Analog Devices

부품명 ADE7166ASTZF16
상세설명  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  144 Pages
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ADE7566/ADE7569/ADE7166/ADE7169
Rev. A | Page 66 of 144
Integration Time Under Steady Load: Reactive Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VARGAIN and VARDIV registers set to
0x000, the integration time before the reactive energy register
overflows is calculated in Equation 26.
Time
=
min
82
.
6
sec
6
.
409
s
22
.
1
0xCCCCD
FFFF
FFFF,
0xFFFF,
=
=
μ
×
(26)
When VARDIV is set to a value different from 0, the integration
time varies, as shown in Equation 27.
VARDIV
Time
Time
WDIV
×
=
=0
(27)
POS
POS
INTERRUPT STATUS REGISTERS
NEG
APSIGN FLAG
ACTIVE POWER
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
REACTIVE ENERGY
NO-LOAD
THRESHOLD
REACTIVE POWER
NO-LOAD
THRESHOLD
Reactive Energy Accumulation Modes
VAR Signed Accumulation Mode
The ADE7569/ADE7169 reactive energy default accumulation
mode is a signed accumulation based on the reactive power
information.
VAR Antitamper Accumulation Mode
The ADE7569/ADE7169 are placed in VAR antitamper
accumulation mode by setting the SAVARM bit in the ACCMODE
register (0x0F). In this mode, the reactive power is accumulated
depending on the sign of the active power. When active power
is positive, the reactive power is added as it is to the reactive
energy register. When active power is negative, the reactive
power is subtracted from the reactive energy accumulator (see
Figure 72. Reactive Energy Accumulation in
Antitamper Accumulation Mode
Figure 72). The CF pulse also reflects this accumulation method
when in this mode. The default setting for this mode is off.
Transitions in the direction of power flow and no-load threshold
are active in this mode.



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