ADE7166ASTZF16 datasheet(88/144 Pages) AD

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ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 88 of 144

DUAL DATA POINTERS

Each ADE7566/ADE7569/ADE7166/ADE7169 incorporates

two data pointers. The second data pointer is a shadow data

pointer and is selected via the Data Pointer Control SFR (DPCON,

0xA7). DPCON features automatic hardware postincrement and

postdecrement, as well as an automatic data pointer toggle.

Note that this section of the data sheet is the only place where

the main and shadow data pointers are distinguished. Whenever

the data pointer (DPTR) is mentioned elsewhere in the data

sheet, active DPTR is implied.

In addition, only the MOVC/MOVX @DPTR instructions

automatically postincrement and postdecrement the DPTR.

Other MOVC/MOVX instructions, such as MOVC PC

or MOVC @Ri, do not cause the DPTR to automatically

postincrement and postdecrement.

To illustrate the operation of DPCON, the following code copies

256 bytes of code memory at Address 0xD000 into XRAM,

starting from Address 0x0000:

MOV DPTR,#0

;Main DPTR = 0

MOV DPCON,#55H

;Select shadow DPTR

;DPTR1 increment mode

;DPTR0 increment mode

;DPTR auto toggling ON

MOV DPTR,#0D000H

;DPTR = D000H

MOVELOOP: CLR A

MOVC A,@A+DPTR

;Get data

;Post Inc DPTR

;Swap to Main DPTR(Data)

MOVX @DPTR,A

;Put ACC in XRAM

;Increment main DPTR

;Swap Shadow DPTR(Code)

MOV A, DPL

JNZ MOVELOOP

Table 66. Data Pointer Control SFR (DPCON, 0xA7)

Bit

Mnemonic

Default

Description

Not Implemented. Write Don’t Care.

DPT

Data Pointer Automatic Toggle Enable. Cleared by the user to disable autoswapping of the DPTR.

Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.

DP1m1,

DP1m0

Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation,

allowing more compact and more efficient code size and execution.

DP1m1

DP1m0

Result (Behavior of the Shadow Data Pointer)

8052 behavior.

DPTR is postincremented after a MOVX or a MOVC instruction.

DPTR is postdecremented after a MOVX or MOVC instruction.

5, 4

DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be

useful for moving 8-bit blocks to/from 16-bit devices.

DP0m1,

DP0m0

Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing

more compact and more efficient code size and execution.

DP0m1

DP0m0

Result (Behavior of the Main Data Pointer)

8052 behavior.

DPTR is postincremented after a MOVX or a MOVC instruction.

DPTR is postdecremented after a MOVX or MOVC instruction.

3, 2

DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful

for moving 8-bit blocks to/from 16-bit devices.

Not Implemented. Write Don’t Care.

DPSEL

Data Pointer Select. Cleared by the user to select the main data pointer, meaning that the contents of

this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data

pointer, meaning that the contents of a separate 16-bit register appear in the DPL SRF and DPH SFR.

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