BD9DA00MF datasheet(44/53 Pages) ROHM

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BD9DA00MF

Datasheet

TSZ02201-0J2J0AB01940-1-2

18.Mar.2025 Rev.001

www.rohm.com

TSZ22111 • 15 • 001

PCB Layout Design – continued

When designing the PCB layout, pay attention to the following points:

•Connect the input capacitors CIN1, CIN2, CIN3, CIN4 and CIN5 as close to the VIN pin and PGND pin as possible on the same

plane as the IC.

•Place two VIN VIAs and two PGND VIAs for CIN2.

•Place as many VIN VIAs as possible directly under the IC to improve heat dissipation.

•Place a minimum of six PGND VIAs near the PGND pins of the IC.

•Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the inductor pattern L as

thick and as short as possible.

•Feedback line connected to the FB pin far from the SW nodes.

•Place RUP, RDOWN, CFB, and CRGND as close to the IC on the same layer as possible to minimize the distance of the feedback

line.

•Place the output capacitors COUT1, COUT2, COUT3, and COUT4 away from the input capacitors CIN1, CIN2, CIN3, CIN4, and CIN5 to

avoid the influence of harmonic noise from the input.

•Separate the reference ground and power ground and connect each with VIAs. Connect the reference ground to the power

ground near CVCC, where high frequency switching noise is minimal.

•Place the VCC bypass capacitor as close to the pin as possible.

CVCC

CBST

RILIM

CSS2

CRGND

RDOWN

COUT1

COUT2

COUT3

COUT4

PGND

VOUT

VIN

Figure 90. Recommended PCB Layout

BD9DA00MF 데이터시트(PDF) 44 Page - Rohm