W137

Rev 1.0, November 24, 2006

Page 2 of 8

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

CPU0:1

24, 23

O

CPU Clock Outputs 0 and 1. These two CPU clock outputs are controlled by the

CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to

PCI1:5

5, 6, 9, 10, 11

O

PCI Bus Clock Outputs 1 through 5. These five PCI clock outputs are controlled by

the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to

PCI_F

4

O

Fixed PCI Clock Output. Unlike PCI1:5 outputs, this output is not controlled by the

PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage

CPU_STOP#

18

I

CPU_STOP# Input. When brought LOW, clock outputs CPU0:1 are stopped LOW

after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,

clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).

PCI_STOP#

20

I

PCI_STOP# Input. The PCI_STOP# input enables the PCI1:5 outputs when HIGH

and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched

on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.

REF0/SEL48#

27

I/O

I/O Dual-Function REF0 and SEL48# Pin. Upon power-up, the state of SEL48# is

will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that

produces a copy of 14.318 MHz.

REF1/SPREAD#

26

I/O

I/O Dual-Function REF1 and SPREAD# Pin. Upon power-up, the state of SPREAD#

Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that produces

a copy of 14.318 MHz.

24/48MHz/OE

14

I/O

I/O Dual-Function 24 MHz or 48 MHz Output and Output Enable Input. Upon

power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to

ms, the pin becomes an output whose frequency is set by the state of pin 27 on

power-up.

48MHz

13

O

48 MHz Output. Fixed 48 MHz USB output. Output voltage swing is controlled by

voltage applied to VDDQ3.

SEL100/66#

16

I

Frequency Selection Input. Select power-up default CPU clock frequency as shown

X1

2

I

Crystal Connection or External Reference Frequency Input. This pin can either be

used as a connection to a crystal or to a reference signal.

X2

3

I

Crystal Connection. An input connection for an external 14.318 MHz crystal. If using

an external reference, this pin must be left unconnected.

PWR_DWN#

17

I

Power Down Control. When this input is LOW, device goes into a low-power standby

condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW

after completing a full clock cycle (2–3 CPU clock cycle latency). When brought

HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency

(3 ms maximum latency).

VDDQ3

8, 12, 19, 28

P

Power Connection. Connected to 3.3V.

VDDQ2

25

P

Power Connection. Power supply for CPU0:1 output buffers. Connected to 2.5V.

GND

1, 7, 15, 21, 22

G

Ground Connection. Connect all ground pins to the common system ground plane.