W137

Rev 1.0, November 24, 2006

Page 7 of 8

PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.

Period

Measured on rising edge at 1.5V

30

ns

High Time

Duration of clock cycle above 2.4V

12.0

ns

Low Time

Duration of clock cycle below 0.4V

12.0

ns

Output Rise Edge Rate Measured from 0.4V to 2.4V

1

4

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

1

4

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum difference

of cycle time between two adjacent cycles.

250

ps

Output Skew

Measured on rising edge at 1.5V

500

ps

CPU to PCI Clock Offset Covers all CPU/PCI outputs. Measured on rising edge

at 1.5V. CPU leads PCI output.

1.5

4.0

ns

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached within 1 ms from

power-up. Short cycles exist prior to frequency stabili-

zation.

3

ms

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

20

REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Max.

Typ.

f

Frequency, Actual

Determined by crystal oscillator frequency

14.318

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

2

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

2

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization from

Power-up (cold start)

Assumes full supply voltage reached within 1 ms

from power-up. Short cycles exist prior to

frequency stabilization.

3

ms

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

48 MHz and 24 MHz Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.6/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Determined by PLL divider ratio (see n/m below)

48.008

24.004

MHz

Deviation from 48 MHz

(48.008 – 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17, 57/34

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

2

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

2

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization from

Power-up (cold start)

Assumes full supply voltage reached within 1 ms

from power-up. Short cycles exist prior to frequency

stabilization.

3

ms

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

25