WM8941GEFLSLASHV datasheet(63/96 Pages) WOLFSON

63 / 96 page

Pre Production

WM8941

PP, Rev 3.3, December 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Table 46 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8941 has an on-chip phase-locked loop (PLL) circuit that can be used to:

•

Generate master clocks for the WM8940 audio functions from another external clock, e.g.

in telecoms applications.

•

Generate an output clock, on GPIO, for another part of the system (derived from an

existing audio master clock).

Table 47 shows the PLL and internal clocking arrangement on the WM8941.

The PLL is enabled or disabled by the PLLEN register bit.

Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are

set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

Management 1

PLLEN

PLL enable

0=PLL off

1=PLL on

Table 47 PLLEN Control Bit

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