AT25DF021A-DWFHT datasheet(11/59 Pages) RENESAS

11 / 59 page

DS-AT25DF021A-042 Rev. L

Page 11

8/7/23

AT25DF021A Datasheet

Device Operation

The AT25DF021A is controlled by a set of commands that are sent from a host controller, commonly referred to as

the SPI Master. The SPI Master communicates with the AT25DF021A through the SPI bus which is comprised of

four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect

to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The

AT25DF021A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI

Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby

mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK

and always output on the falling edge of SCK.

Figure 7. SPI Mode 0 and 3

5.1

Dual Output Read

The AT25DF021A features a Dual-Output Read mode that allow two bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, both the SI and SO pins are used as outputs for the transfer of

data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

SCK

MSB

LSB

MSB

LSB

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