M95256 datasheet(18/43 Pages) STMICROELECTRONICS

18 / 43 page

Instructions

M95256, M95256-W, M95256-R

18/43

5.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

previously executed. After the Write Enable (WREN) instruction has been decoded and

executed, the Status Register is updated with the Write Enable Latch bit (WEL) set to 1.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

followed by the instruction code and the data byte on Serial Data input (D). The instruction is

terminated by driving Chip Select (S) high at a byte boundary of the input data. This event

triggers the self-timed write cycle, and continues for a period tW (as specified in Table 16,

Table 17, Table 18 and Table 19), at the end of which the Write in Progress (WIP) bit is reset

to 0.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

Status Register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in

the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,

the Write Status Register (WRSR) instruction is not executed.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Write Status Register cycle tW, and is 0 when it is completed. When the

cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-

only, as defined in Table 4.

The Write Status Register (WRSR) instruction also allows the user to set or reset the Status

Status Register Write Disable (SRWD) bit and Write Protect (W) signal can be used to put

the device in the Hardware-protected mode (HPM, see Table 5). In this mode, the Write

Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the Write

Status Register (WRSR) instruction, including the tW Write cycle.

The instruction sequence is shown in Figure 8.

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