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AT45DB641E 데이터시트(PDF) 10 Page - Renesas Technology Corp |
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AT45DB641E 데이터시트(HTML) 10 Page - Renesas Technology Corp |
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10 / 78 page ![]() DS-AT45DB641E-027 Rev. O Page 10 6/30/23 © 2023 Renesas Electronics AT45DB641E Datasheet 4. Memory Array To provide optimal flexibility, the AT45DB641E memory array is divided into three levels, comprising sectors, blocks, and pages. Figure 3 shows each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3. Memory Architecture Diagram Sector 0a = 8 pages 2,048/2,112 bytes Sector 0b = 1,016 pages 260,096/268,224 bytes Block = 2,048 / 2,112 bytes 8 Pages Sector 0a Page = 256 / 264 bytes Page 0 Page 1 Page 6 Page 7 Page 8 Page 9 Page 32,766 Page 32,767 Page 14 Page 15 Page 16 Page 17 Page 18 Sector Architecture Block Architecture Page Architecture Block 0 Block 1 Block 126 Block 127 Block 128 Block 129 Block 4,094 Block 4,095 Block 254 Block 255 Block 256 Block 257 Sector 31 = 1,024 pages 262,144/270,366 bytes Block 2 Sector 1 = 1,024 pages 262,144/270,336 bytes Sector 30 = 1,024 pages 262,144/270,336 bytes Sector 2 = 1,024 pages 262,144/270,336 bytes |
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