MPC8245 datasheet(61/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Document Revision History

0.1

—

Made VDD/AVDD/AVDD2 = 1.8 V ± 100 mV information for 133-MHz memory interface operation to

Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2.

Pin D17, formerly LAVDD (supply voltage for DLL), is a NC on the MPC8245 since the DLL voltage is

supplied internally. Eliminated all references to LAVDD; updated Section 1.7.1.

Previous Note 4 of Table 2 did not apply to the MPC8245 (MPC8240 document legacy). New Note 4

added in reference to maximum CPU speed at reduced VDD voltage.

Updated the Programmable Output Impedance of DEV_MEM_ADDR in Table 4 to 6

Ω to reflect

characterization data.

Updated Table 5 to reflect reduced power consumption when operating VDD/AVDD/AVDD2 = 1.8 V ±

100 mV. Changed Notes 2, 3, and 4 to reflect VDD at 1.9 V. Changed Note 5 to represent VDD = AVDD

= 1.8 V.

Updated Table 7 to reflect VDD/AVDD/AVDD2 voltage level operating frequency dependencies;

changed 250 MHz device column to 266 MHz; modified Note 1 eliminating VCO references; added

Note 2. Changed 250 MHz processor frequency offering to 266 MHz.

Changed Spec 12b for memory output valid time in Table 11 from 5.5 ns to 4.5 ns; this is a key

specification change to enable 133-MHz memory interface designs.

Updated Pinout Table 16 with the following changes:

• Pin types for RCS0, RCS3/TRIG_OUT and DA[11:15] were erroneously listed as I/O, changed Pin

Types to Output.

• Pin types for REQ4/DA4, RCS2/TRIG_IN, and PLL_CFG[0:4]/DA[10:6] were erroneously listed as

Input, changed Pin Types to I/O.

• Changed Pin D17 from LAVDD to No Connect; deleted Note 21 and references.

• Notes 3, 5, and 7 contained references to the MPC8240 (MPC8240 document legacy); changed

these references to MPC8245.

• Previous Notes 13 and 14 did not apply to the MPC8245 (MPC8240 document legacy), these notes

were deleted; moved Note 19 to become new Note 13; moved Note 20 to become new Note 14;

updated associated references.

• Added Note 3 to SDMA[1:0] signals about internal pull-up resistors during reset state.

• Reversed vector ordering for the PCI Interface Signals: C/BE[0:3] changed to C/BE[3:0], AD[0:31]

changed to AD[31:0], GNT[0:3] changed to GNT[3:0], and REQ[0:3] changed to REQ[3:0]. The

package pin number orderings were also reversed meaning that pin functionality did NOT change.

For example, AD0 is still on signal C22, AD1 is still on signal D22,..., AD31 is still on signal V25. This

change was made to make the vectored PCI signals in this hardware specification consistent with

the PCI Local Bus Specification and the MPC8245 Integrated Processor Reference Manual vector

ordering.

• Changed TEST1/DRDY signal on pin B20 to DRDY.

• Changed TEST2 signal on pin Y2 to RTC for performance monitor use.

Updated PLL Table 17 with the following changes for 133-MHz memory interface operation:

• Added Ref. 9 (01001) and Ref. 17 (10111) details; removed these settings from Note 10 (reserved

settings list).

• Enhanced range of Ref. 10 (10000).

• Updated Note 13, changed bits 16–20 erroneous information to correct bits 23–19.

• Added Notes 16 and 17.

Added information to Section 1.7.8 in reference to CHKSTOP_IN and SRESET being unavailable in

extended ROM mode.

0.0

—

Initial release.

Table 19. Revision History Table (continued)

Revision

Date

Substantive Change(s)

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