PIC16F87X datasheet(73/200 Pages) MICROCHIP

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PIC16F87X

Preliminary

DS30292A-page 73

9.2.1.2

SLAVE RECEPTION

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overﬂow condition exists, then

no acknowledge (ACK) pulse is given. An overﬂow con-

dition is deﬁned as either bit BF (SSPSTAT<0>) is set

or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the received byte.

TABLE 9-2

DATA TRANSFER RECEIVED BYTE ACTIONS

9.2.1.3

SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and the SCL pin is held low.

The transmit data must be loaded into the SSPBUF

SCL pin should be enabled by setting bit CKP (SSP-

CON<4>). The master must monitor the SCL pin prior

to asserting another clock pulse. The slave devices

may be holding off the master by stretching the clock.

The eight data bits are shifted out on the falling edge of

the SCL input. This ensures that the SDA signal is valid

during the SCL high time (Figure 9-13).

An SSP interrupt is generated for each data transfer

byte. The SSPIF ﬂag bit must be cleared in software,

and the SSPSTAT register is used to determine the sta-

tus of the byte transfer. The SSPIF ﬂag bit is set on the

falling edge of the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then the

data transfer is complete. When the not ACK is latched

by the slave, the slave logic is reset and the slave then

monitors for another occurrence of the START bit. If the

SDA line was low (ACK), the transmit data must be

loaded into the SSPBUF register, which also loads the

SSPSR register. Then the SCL pin should be enabled

by setting the CKP bit.

FIGURE 9-12: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Note:

The SSPBUF will be loaded if the SSPOV

bit is set and the BF ﬂag is cleared. If a

read of the SSPBUF was performed, but

the user did not clear the state of the

SSPOV

bit

before

the

receive

occurred. The ACK is not sent and the

SSPBUF is updated.

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overﬂow condition.

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

Not

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