ST7LITEU09 datasheet(98/115 Pages) STMICROELECTRONICS

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13.10 10-BIT ADC CHARACTERISTICS

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. The maximum ADC clock frequency allowed within VDD = 2.4V to 2.7V operating range is 1MHz.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maxi-

mum value). Data guaranteed by Design, not tested in production.

4. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then

always valid.

Figure 68. Typical Application with ADC

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

fADC

ADC clock frequency 2)

4MHz

VAIN

Conversion voltage range

VSS

VDD

RAIN

External input resistor

VDD = 5V, fADC=4MHz

8k 3)

Ω

VDD = 3.3V, fADC=4MHz

7k 3)

2.7V

≤ V

DD ≤5.5V, fADC=2MHz

10k 3)

2.4V

≤ V

DD ≤2.7V, fADC=1MHz

20k 3)

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

fCPU=8MHz, fADC=4MHz

0 4)

µs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

AINx

ST7LITEU0x

VDD

±1

µA

0.6V

CADC

VAIN

RAIN

10-Bit A/D

Conversion

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