ST7LITEU09 datasheet(24/115 Pages) STMICROELECTRONICS

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7.2 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by

hardware after a reset. This bit allows to enable

the MCO output clock.

0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the input

clock fOSC or fOSC/32.

0: Normal mode (fCPU = fOSC

1: Slow mode (fCPU = fOSC/32)

RC CONTROL REGISTER (RCCR)

Read / Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-

justment Bits

These bits, as well as CR[1:0] bits in the SICSR

adjust the RC oscillator frequency and to obtain

the required accuracy. The application can store

the correct value for each voltage range in Flash

memory and write it to this register at start-up.

00h = maximum available frequency

FFh = lowest available frequency

Note: To tune the oscillator, write a series of differ-

ent values in the register until the correct frequen-

cy is reached. The fastest method is to use a di-

chotomy starting with 80h.

SYSTEM INTEGRITY (SI) CONTROL/STATUS

Read/Write

Reset Value: 0000 0x00 (0xh)

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

adjust the RC oscillator frequency and to obtain

the required accuracy. Refer to section 7.1 on

page 22.

Bits 4:3 = Reserved, must be kept cleared.

Bits 2:0 = System Integrity bits. Refer to Section

8.4 SYSTEM INTEGRITY MANAGEMENT (SI).

MCO SMS

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1 CR0

LVDRF AVDF AVDIE

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