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TDA7500A 데이터시트(PDF) 19 Page - STMicroelectronics |
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TDA7500A 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 40 page ![]() 19/40 TDA7500A SAI INTERFACE Figure 1. SAI Timings Note TDSP = dsp master clock cycle time = 1/FDSP Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 Timing Description Value Unit tsckr Minimum Clock Cycle 4TDSP ns tdt SCKR active edge to data out valid 10 ns tlrs LRCK setup time 5 ns tlrh LRCK hold time 5 ns tsdid SDI setup time 15 ns tsdih SDI hold time 15 ns tsckph Minimum SCK high time 0.35 tsckr ns tsckpl Minimum SCK low time 0.35 tsckr ns SDI0-3 LRCKR SCKR (RCKP=0) t lrh tsdis tsdih tlrs t sckpl tsckph Valid Valid tdt t sckr LEFT RIGHT LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) LRCKR (#68) SCKR (#67) SDI0,1,2 (#62, #63, #64) |
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