PM6670 datasheet(24/53 Pages) STMICROELECTRONICS

24 / 53 page

Device description

PM6670

24/53

The design of the external feedback network depends on the output voltage ripple. If the

ripple is higher than approximately 20mV, the correct CINT capacitor is usually enough to

keep the loop stable. The stability of the system depends firstly on the output capacitor zero

frequency.

The following condition must be satisfied:

Equation 6

where k is a fixed design parameter (k > 3). It determines the minimum integrator capacitor

value:

Equation 7

where gm = 50

µs is the integrator trans conductance.

In order to ensure stability it must be also verified that:

Equation 8

If the ripple on the COMP pin is greater than the integrator 150mV, the auxiliary capacitor

CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given

by:

Equation 9

In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that,

together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be

much greater (10 or more times) than the switching frequency:

Equation 10

If the ripple is very small (lower than approximately 20mV), a different compensation

network, called "Virtual-ESR" Network, is needed. This additional circuit generates a

triangular ripple that is added to the output voltage ripple at the input of the integrator. The

complete control scheme is shown in Figure 32.

ESR

out

Zout

⋅

Vout

Zout

INT

⋅

⎟

⎠

⎞

⎜

⎝

⎛

−

⋅

OUT

Zout

INT

⋅

)

(

INT

FILT

−

⋅

FILT

INT

FILT

INT

CUT

INT

⋅

PM6670 데이터시트(PDF) 24 Page - STMicroelectronics

PM6670 데이터시트(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

데이터시트 다운로드

링크 URL