M29F512B

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Unlock Bypass Program Command. The

Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write operations, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. The

operation cannot be aborted and the Status Reg-

ister is read. Errors must be reset using the Read/

Reset command, which leaves the device in Un-

lock Bypass Mode. See the Program command for

details on the behavior.

Unlock Bypass Reset Command. The

Unlock

Bypass Reset command can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the memory. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

All Bus Read operations during the Chip Erase op-

eration will output the Status Register on the Data

Inputs/Outputs. See the section on the Status

Register for more details. Typical chip erase times

are given in Table 5.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase command sets all of the bits in the

memory to ’1’. All previous data is lost.

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 6, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion. The Data Polling Bit is output on DQ7 when

the Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

Figure 3, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or any

address while erasing the chip.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation. The Toggle

Bit is output on DQ6 when the Status Register is

read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

Figure 4, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Table 5. Program, Erase Times and Program, Erase Endurance Cycles

Parameter

Min

Typical after

Max

Unit

Chip Erase (All bits in the memory set to ‘0’)

0.4

0.4

sec

Chip Erase

0.8

0.8

4

sec

Program

8

8

150

µs

Chip Program

0.6

0.6

2.5

sec

Program/Erase Cycles

100,000

cycles