PDSP1601/PDSP1601A

12

Function

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

R1 register will be loaded with the data present on the SV port. The input to the Barrel

Shifter will be passed onto the output unshifted.

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

R2 register will be loaded with the data present on the SV port. The input to the Barrel

Shifter will be passed onto the output unshifted.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number present in the SV register. The LSBs are discarded,

and the vacant MSBs are filled with duplicates of the original MSB. (Sign Extension).

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R1 register. The LSBs are

discarded, and the vacant MSBs are filled with duplicates of the original MSB.

(Sign Extension).

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R2 register. The LSBs are

discarded, and the vacant MSBs are filled with duplicates of the original MSB.

(Sign Extension).

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number output from the Priority Encoder. This value is also output

on the SV port (provided SVOE is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number output from the Priority Encoder. This value is also loaded

into the R1 register at the end of the cycle, and is output on the SV port (provided SVOE

is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number output from the Priority Encoder. This value is also loaded

into the R2 register at the end of the cycle, and is output on the SV port (provided SVOE

is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

Op Code

<8>

<9>

<A>

<B>

<C>

<D>

<E>

<F>

Mnemonic

LR1SV

LR2SV

ASRSV

ASRR1

ASRR2

NRMXX

NRMR1

NRMR2