LXT362 datasheet(21/48 Pages) INTEL

부품명	LXT362

상세설명	Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

PDF	48 Pages

Scroll/Zoom	100%

제조업체	INTEL [Intel Corporation]

홈페이지	http://www.intel.com

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21 / 48 page

Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362

Datasheet

2.7.1

Loopback Modes

2.7.1.1

Local Loopback (LLOOP)

See Figure 5 and Figure 6. LLOOP inhibits the receiver circuits. The transmit clock and data inputs

(TCLK and TPOS/TNEG or TDATA) loop back through the jitter attenuator (if enabled) and

appear at RCLK and RPOS/RNEG or RDATA. Note that during LLOOP, the JASEL input is

strictly an enable/disable control, i.e. it does not affect the placement of the JA. If the JA is enabled,

it is active in the loopback circuit. If the JA is bypassed, it is not active in the loopback circuit.

The transmitter circuits are unaffected by LLOOP and the LXT362 continues to transmit the

TPOS/TNEG or TDATA inputs (or a stream of 1’s if TAOS is asserted). When used in this mode,

the transceiver can function as a stand-alone jitter attenuator.

In Hardware mode, Local loopback (LLOOP) is selected by setting LLOOP High; in Host mode,

by setting bit CR2.ELLOOP = 1.

Figure 5. TAOS with LLOOP

LXT362 데이터시트(PDF) 21 Page - Intel Corporation