STA328 datasheet(9/57 Pages) STMICROELECTRONICS

9 / 57 page

STA328

Pin out

9/57

2.3

Pin description

OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)

Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the

speakers.

RESET (pin 22)

Driving RESET low sets all outputs low and returns all register settings to their default

(reset) values. The reset is asynchronous to the internal clock.

I/O

VCC1A

Positive supply

OUT1A

Output half bridge 1A

I/O

GND_CLEAN

Logical ground

I/O

GND_REG

Substrate ground

I/O

VDD_REG

Logic supply

I/O

Logic supply

CONFIG

Logic levels

RESET

Reset

SCL

I2C serial clock

I/O

SDA

I2C serial data

RESERVED

This pin must be connected to GND

PLL_FILTER

Connection to PLL filter

XTI

PLL input clock

I/O

GNDA

Analog ground

I/O

VDDA

Analog supply, nominally 3.3 V

SDI

I2S serial data channels 1 & 2

I/O

LRCKI

I2S left/right clock,

BICKI

I2S serial clock

I/O

GND

Digital ground

I/O

VDD

Digital supply, nominally 3.3 V

I/O

VSS

5 V regulator referred to +VCC

I/O

VCC_SIGN

5 V regulator referred to ground

Table 2.

Pin list

Number

Type

Name

Description

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