LAN9312 datasheet(94/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9312

DATASHEET

For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and

asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for

100BASE-TX, or 2.5MHz for 10BASE-T.

For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are

clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the

output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If

there is no received signal, it is derived from the system reference clock.

7.2.8

PHY Management Control

The PHY Management Control block is responsible for the management functions of the PHY,

including register access and interrupt generation. A Serial Management Interface (SMI) is used to

support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific

registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO)

signal and the MII Management Clock (MDC) signal. These signals interface to the Host MAC and

allow access to all PHY registers. Refer to Section 14.4.2, "Port 1 & 2 PHY Registers," on page 286

for a list of all supported registers and register descriptions. Non-supported registers will be read as

FFFFh.

7.2.8.1

PHY Interrupts

The PHY contains the ability to generate various interrupt events as described in Table 7.3. Reading

the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of

the interrupt, and clears the interrupt signal. The Port x PHY Interrupt Mask Register

(PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt. The PHY Management Control

block aggregates the enabled interrupts status into an internal signal which is sent to the System

Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bit 26 (PHY_INT1) for

the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9312

interrupts, refer to Chapter 5, "System Interrupts," on page 49.

7.2.9

PHY Power-Down Modes

There are two power-down modes for the PHY:

PHY General Power-Down

PHY Energy Detect Power-Down

Note:

For more information on the various power management features of the LAN9312, refer to

Section 4.3, "Power Management," on page 46.

Table 7.3 PHY Interrupt Sources

INTERRUPT SOURCE

PHY_INTERRUPT_MASK_x &

PHY_INTERRUPT_SOURCE_x REGISTER BIT #

ENERGYON Activated

Auto-Negotiation Complete

Remote Fault Detected

Link Down (Link Status Negated)

Auto-Negotiation LP Acknowledge

Parallel Detection Fault

Auto-Negotiation Page Received

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