JS48F4400P0P3C0 datasheet(79/139 Pages) NUMONYX

79 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

Notes:

Address latched on valid clock edge with ADV# low and LC count begins.

Address latched on ADV# rising edge. LC count begins on subsequent valid CLK edge.

9.3

Enhanced Configuration Register

The Enhanced Configuration Register (ECR) is a volatile 16-bit, read/write register used

to select Deep Power Down (DPD) operation and to modify the output-driver strength

of the flash device. All Enhanced Configuration Register bits are set and cleared using

the Program Enhanced Configuration Register command. Upon power-up or exit from

reset, the Enhanced Configuration Register defaults to 0004h.

To read the value of the ECR, issue the Read Device Information command to the

desired partition. Subsequent reads from the <partition base address> + 06h returns

ECR[15:0].

Figure 46: Latency Count Period

ADV#-Latch (2)

CLK Latch (1)

tCHQV

Latency Count

CLK

ADV# (1)

ADV# (2)

A[Max:0]

CE#

OE#

DQ[15:0]

Table 32: CLK Frequencies for LC Settings

VCCQ = 1.7 V to 2.0 V

Latency Count Setting

Frequency Supported (MHz)

≤ 32.6 MHz

≤ 43.5 MHz

≤ 54.3 MHz

≤ 65.2 MHz

≤ 76.1 MHz

≤ 87 MHz

≤ 97.8 MHz

≤ 108.7 MHz

≤ 119.6 MHz

≤ 130.4 MHz

≤ 133.3 MHz

JS48F4400P0P3C0 데이터시트(PDF) 79 Page - Numonyx B.V

JS48F4400P0P3C0 데이터시트(HTML) 79 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL