STMPE801

I2C module

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5

STMPE801 is interface to the main processor using an I2C bus.

5.1

Addressing scheme of STMPE801 is designed to allow up to 2 devices to be connected to

Figure 3.

Addressing scheme

For the bus master to communicate to the slave device, the bus master must initiate a Start

condition anf followed by the slave device address. Accompanying the slave device address,

there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for write operation.

If a match occurs on the slave device address, the corresponding device gives an

the bus by not responding to the transaction.

Table 6. Addresses

ADDR0

Address

Note

0

0x82

1

0x88