M58LW064 datasheet(32/53 Pages) STMICROELECTRONICS

32 / 53 page

M58LW064A, M58LW064B

32/53

Table 25. Synchronous Burst Read

(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDD = 1.8V to VDD)

Note: 1. Data output should be read on the valid clock edge.

2. For paramters not listed see Asynchronous Read.

Symbol(2)

Parameter

Test Condit ion

Min

Max

Unit

tAVLL

Address Valid to Latch Enable Low

E= VIL

tBHKH

Burst Address Advance High toValid Clock Edge

E = VIL,G = VIL,L = VIH

tBLKH

Burst Address Advance Low to Valid Clock Edge

E= VIL,G = VIL,L = VIH

tELLL

Chip Enable Low to Latch Enable low

tGLKH

Output Enable Low to Valid Clock Edge

E=VIL,L = VIH

tKHAX

Valid Clock Edge to Address Transition

E= VIL

0ns

tKHLL

Valid Clock Edge to Latch Enable Low

E= VIL

0ns

tKHLX

Valid Clock Edge to Latch Enable Transition

E= VIL

0ns

tKHQX

Valid Clock Edge to Output Transition

E= VIL,G = VIL,L = VIH

6ns

tLLKH

Latch Enable Low to Valid Clock Edge

E= VIL

tQVKH

(1)

Output Valid to Valid Clock Edge

E= VIL,G = VIL,L = VIH

tRLKH

Valid Data Ready Low to Valid Clock Edge

E= VIL,G = VIL,L = VIH

Figure 12. Synchronous Burst Read (9.1.1.1 example)

X-Latency = 0 (M14-M11 = 0100), Y-Latency = 1 (M9 = 0), Burst Length = 4 (M2-M0 = 001),

Burst Type = Sequential (M7 = 1), Valid Clock Edge = Rising (M6 = 1)

AI03698

(1)

For set up signals and timings see Synchronous Burst Read 8.1.1.1

DQ0-DQx

tQVKH

tKHQX

SETUP

(1)

Burst Read

Q0 to Q3

Burst Read Wraps if Device

remains Selected (E = VIL)

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