RA2E2 datasheet(39/101 Pages) RENESAS

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Table 2.31

SCI timing (2) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Max

Unit*1

Test

conditions

Simple

SPI

Slave access time

2.4 V ≤ VCC ≤ 5.5 V

tSA

—

tPcyc

Figure 2.26

1.8 V ≤ VCC < 2.4 V

24 MHz ≤ PCLKB ≤

32 MHz

—

PCLKB < 24 MHz

—

1.6 V ≤ VCC < 1.8 V

—

Slave output release time 2.4 V ≤ VCC ≤ 5.5 V

tREL

—

tPcyc

1.8 V ≤ VCC < 2.4 V

24 MHz ≤ PCLKB ≤

32 MHz

—

PCLKB < 24 MHz

—

1.6 V ≤ VCC < 1.8 V

—

Note 1. tPcyc: PCLKB cycle.

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

SCKn

master select

output

SCKn

slave select input

Note:

n = 9

Figure 2.22

SCI simple SPI mode clock timing

RA2E2 Datasheet

2. Electrical Characteristics

R01DS0387EJ0150 Rev.1.50

Nov 8, 2025

Page 39 of 101

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