RA2E2 datasheet(60/101 Pages) RENESAS

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SDA

Timing

parameters

used

0.3 × VDD

0.7 × VDD

Active Drive by Master

Note :

Master releases or drives SDA after a

suitable delay from SCL edges

NM_SDA

CM_SDA

NM_SCL

CM_SCL

SCL

tSU_STO

tMMlock

tMMoverlap

tCAS

tSCO

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

OD or PP

Open-Drain

OD or PP

Open-Drain

Open-Drain class Pull-Up by master

High-Z by Master

Figure 2.44

I3C Timing

2.3.11

CLKOUT Timing

Table 2.39

CLKOUT timing

Parameter

Symbol

Min

Max

Unit

Test conditions

CLKOUT

CLKOUT pin output cycle*1

2.7 V ≤ VCC ≤ 5.5 V

tCcyc

62.5

—

Figure 2.45

1.8 V ≤ VCC < 2.7 V

125

—

1.6 V ≤ VCC < 1.8 V

250

—

CLKOUT pin high pulse

width*2

2.7 V ≤ VCC ≤ 5.5 V

tCH

—

1.8 V ≤ VCC < 2.7 V

—

1.6 V ≤ VCC < 1.8 V

150

—

CLKOUT pin low pulse

width*2

2.7 V ≤ VCC ≤ 5.5 V

tCL

—

1.8 V ≤ VCC < 2.7 V

—

1.6 V ≤ VCC < 1.8 V

150

—

CLKOUT pin output rise time

2.7 V ≤ VCC ≤ 5.5 V

tCr

—

1.8 V ≤ VCC < 2.7 V

—

1.6 V ≤ VCC < 1.8 V

—

CLKOUT pin output fall time

2.7 V ≤ VCC ≤ 5.5 V

tCf

—

1.8 V ≤ VCC < 2.7 V

—

1.6 V ≤ VCC < 1.8 V

—

RA2E2 Datasheet

2. Electrical Characteristics

R01DS0387EJ0150 Rev.1.50

Nov 8, 2025

Page 60 of 101

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