AS1130-BSST datasheet(44/67 Pages) AMSOSRAM

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ams Datasheet

Page 43

[v2-01] 2016-Oct-12

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AS1130 − Register Description

Note(s):

1. This configuration is locked after the first write access to ON/OFF, PWM od DotCorrection data section. Unlock can be performed

only by a reset of the device.

Interrupt Mask Register (0x07)

Per default this register is set to 0x20.

Figure 46:

Interrupt Mask Register Format

common_addr

R/W

I²C Common Address

0: Disabled

1: Enabled (all AS1130 are reacting on the same

address “0111111”)

2:0

mem_conf

000

R/W

Define Memory Configuration(1)

(see RAM Configuration)

000: Invalid Configuration (default value)

001: RAM Configuration 1

010: RAM Configuration 2

011: RAM Configuration 3

100: RAM Configuration 4

101: RAM Configuration 5

110: RAM Configuration 6

0x07 Interrupt Mask Register

Bit

Bit Name

Default

Access

Bit Description

7selected_pic

R/W

IRQ pin triggers if defined frame is displayed (see

Interrupt Frame Definition Register (0x08))

0: Disabled

1: Enabled

6watchdog

R/W

IRQ pin triggers if the I²C watchdog triggers

0: Disabled

1: Enabled

5por

R/W

IRQ pin triggers if POR is active

0: Disabled

1: Enabled

4overtemp

R/W

IRQ pin triggers if the overtemperature limit is

reached

0: Disabled

1: Enabled

3low_vdd

R/W

IRQ pin triggers if VDD is too low for used LEDs

(low_VDD flag)

0: Disabled

1: Enabled

0x06 AS1130 Config Register

Bit

Bit Name

Default

Access

Bit Description

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