RA4M3 datasheet(62/98 Pages) RENESAS

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2.3.12

SSIE Timing

Table 2.31

SSIE timing

(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.

(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Target specification

Unit

Comments

Min.

Max.

SSIBCK0

Cycle

Master

—

Figure 2.44

Slave

—

High level/ low

level

Master

tHC/tLC

0.35

—

Slave

0.35

—

Rising time/

falling time

Master

tRC/tFC

—

0.15

tO / tI

Slave

—

0.15

tO / tI

SSILRCK0/

SSIFS0,

SSITXD0,

SSIRXD0,

SSIDATA0

Input set up

time

Master

tSR

—

Figure 2.46,

Figure 2.47

Slave

—

Input hold time

Master

tHR

—

Slave

—

Output delay

time

Master

tDTR

-10

Slave

Figure 2.46,

Figure 2.47

Output delay

time from

SSILRCK0/

SSIFS0 change

Slave

tDTRW

—

Figure 2.48*1

GTIOC2A,

AUDIO_CLK

Cycle

tEXcyc

—

Figure 2.45

High level/ low level

tEXL/tEXH

0.4

0.6

tEXcyc

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate

transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.

SSIBCK0

tHC

tO, tI

tLC

tRC

tFC

Figure 2.44

SSIE clock input/output timing

RA4M3 Datasheet

2. Electrical Characteristics

R01DS0368EJ0150 Rev.1.50

Apr 25, 2025

Page 62 of 98

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