R7KA8M2ADECAC datasheet(73/295 Pages) RENESAS

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Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. IDD depends on f (ICLK) as follows.

IDD Typ. = 0.02 × fCPUCLK0 + 0.05 × fICLK + 55 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 125℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 704 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 461 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 533 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 125℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 686 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 3. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 4. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

Note 5. Typical DCDC efficiency and the voltage of the test conditions are applied.

Table 2.27

Current of high-speed mode, CPU0 Sleep, CPU1 Deep Sleep (External VDD mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

125 °C

Supply

current

*1*3*4

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VCL = voltage

range 1

IDD*2

505

—

CPU1 = Deep Sleep

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD*2

—

576

—

CPUCLK0 = 600

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD*2

—

703

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VCL = voltage

range 2

IDD*2

477

565

678

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. IDD depends on f (ICLK) as follows.

IDD Typ. = 0.02 × fCPUCLK0 + 0.05 × fICLK + 55 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 95℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 105℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 125℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 704 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 95℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 461 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 105℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 533 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 125℃) = 0.004 × fCPUCLK0 + 0.01 × fICLK + 686 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 3. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 4. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 73 of 295

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