 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
R7KA8M2AFDCAM 데이터시트(PDF) 284 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R7KA8M2AFDCAM 데이터시트(HTML) 284 Page - Renesas Technology Corp |
|
|
284 / 295 page  Appendix 3. I/O Registers This appendix describes I/O register address and access cycles by function. 3.1 Peripheral Base Addresses This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description, and the base address of each peripheral. Table A3.1 Peripheral base address (1 of 4) Description Name of secure registers Base address of secure registers in secure alias region Name of non-secure registers Base address of non-secure registers in non- secure alias region Renesas Memory Protection Unit RMPU 0x4000_0000 RMPU_NS 0x5000_0000 SRAM Control SRAM 0x4000_2000 SRAM_NS 0x5000_2000 BUS Control BUS 0x4000_3000 BUS_NS 0x5000_3000 Common Interrupt Controller ICU_COMMON 0x4000_6000 ICU_COMMON_NS 0x5000_6000 CPU System Security Control Unit CPSCU 0x4000_8000 CPSCU_NS 0x5000_8000 Direct Memory Access Controller 00 DMAC00 0x4000_A000 DMAC00_NS 0x5000_A000 Direct Memory Access Controller 01 DMAC01 0x4000_A040 DMAC01_NS 0x5000_A040 Direct Memory Access Controller 02 DMAC02 0x4000_A080 DMAC02_NS 0x5000_A080 Direct Memory Access Controller 03 DMAC03 0x4000_A0C0 DMAC03_NS 0x5000_A0C0 Direct Memory Access Controller 04 DMAC04 0x4000_A100 DMAC04_NS 0x5000_A100 Direct Memory Access Controller 05 DMAC05 0x4000_A140 DMAC05_NS 0x5000_A140 Direct Memory Access Controller 06 DMAC06 0x4000_A180 DMAC06_NS 0x5000_A180 Direct Memory Access Controller 07 DMAC07 0x4000_A1C0 DMAC07_NS 0x5000_A1C0 DMAC Module Activation 0 DMA0 0x4000_A800 DMA0_NS 0x5000_A800 Data Transfer Controller 0 DTC0 0x4000_AC00 DTC0_NS 0x5000_AC00 Interrupt Controller ICU 0x4000_C000 ICU_NS 0x5000_C000 CPU Control Registers CPU_CTRL 0x4000_F000 CPU_CTRL_NS 0x5000_F000 On-Chip Debug CPU_OCD 0x4001_1000 CPU_OCD_NS 0x5001_1000 Debug Function CPU_DBG 0x4001_B000 CPU_DBG_NS 0x5001_B000 CACHE CACHE 0x4001_C000 CACHE_NS 0x5001_C000 TCM TCM 0x4001_C800 TCM_NS 0x5001_C800 System Control SYSC 0x4001_E000 SYSC_NS 0x5001_E000 Inter-Processor Communication IPC 0x4002_0000 IPC_NS 0x5002_0000 Temperature Sensor Data TSD 0x02C1_EDA0 TSD_NS 0x12C1_EDA0 MRAM System Register area MRAM 0x4013_C000 MRAM_NS 0x5013_C000 Event Link Controller ELC 0x4020_1000 ELC_NS 0x5020_1000 Realtime Clock RTC 0x4020_2000 RTC_NS 0x5020_2000 Independent Watchdog Timer IWDT 0x4020_2200 IWDT_NS 0x5020_2200 Clock Frequency Accuracy Measurement Circuit CAC 0x4020_2400 CAC_NS 0x5020_2400 Watchdog Timer 0 WDT0 0x4020_2600 WDT0_NS 0x5020_2600 Watchdog Timer 1 WDT1 0x4020_2700 WDT1_NS 0x5020_2700 Module Stop Control A, B, C, D, E MSTP 0x4020_3000 MSTP_NS 0x5020_3000 RA8M2 Datasheet Appendix 3. I/O Registers R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 284 of 295 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
