R7KA8M2AFDCAM datasheet(156/295 Pages) RENESAS

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Table 2.60

SCI timing (Simple SPI) (1 of 3)

Condition 1: VCC/VCC2 = 2.70 V or above

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Condition 2: VCC/VCC2 = 1.62 V or above

Following pins have high-speed high-drive output selected in the Port Drive Capability bit in the PmnPFS register: SCK1_A, SCK1_C,

SCK3_A, SCK4_A, SCK4_B, SCK4_C and SCK6_B

Other pins have high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC=VCC2.

Parameter

High

Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

SCK clock cycle

output

Master

—

2.70 V or above

tSPcyc

2 (TCLK ≤ 120MHz)

4 (TCLK >

120MHz)

65536 tTcyc

Figure 2.69

1.62 V or above

2 (TCLK ≤ 60MHz)

4 (TCLK ≤ 120MHz)

8 (TCLK >

120MHz)

65536

SCK clock cycle

input

Slave

—

2.70 V or above

—

1.62 V or above

2 (TCLK ≤ 100MHz)

4 (TCLK >

100MHz)

—

SCK clock high

pulse width

Master

—

1.62 V or above

tSPCKWH

0.4

—

tSPcyc

Slave

—

SCK clock low

pulse width

Master

—

1.62 V or above

tSPCKWL

0.4

—

tSPcyc

Slave

—

SCK clock rise and

fall time

Output

—

2.70 V or above

tSPCKr,

tSPCKf

—

3.3

1.62 V or above

—

6.6

Input

—

2.70 V or above

—

0.1*3

tSPcyc

1.62 V or above

—

0.1*3

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 156 of 295

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