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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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R7KA8M2AFDCAM 데이터시트(PDF) 275 Page - Renesas Technology Corp |
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R7KA8M2AFDCAM 데이터시트(HTML) 275 Page - Renesas Technology Corp |
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275 / 295 page  tSWDS SWCLK tSWDH SWDIO (Input) tSWDD SWDIO (Output) tSWDD SWDIO (Output) tSWDD SWDIO (Output) Figure 2.156 SWD input/output timing 2.19 Embedded Trace Macro Interface (ETM) Table 2.126 ETM (1 of 2) Conditions: High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter VCC Symbol Min Typ Max Unit Test conditions TCLK clock cycle time 2.7 V or above tTCLKcyc 16 — — ns Figure 2.157 1.62 V or above 16 — — ns TCLK clock high pulse width 2.7 V or above tTCLKH 7 — — ns 1.62 V or above 6 — — ns TCLK clock low pulse width 2.7 V or above tTCLKL 7 — — ns 1.62 V or above 6 — — ns TCLK clock rise time 2.7 V or above tTCLKr — — 1.0 ns 1.62 V or above — — 2.0 ns TCLK clock fall time 2.7 V or above tTCLKf — — 1.0 ns 1.62 V or above — — 2.0 ns RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 275 of 295 |
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