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RX72N 데이터시트(PDF) 5 Page - Renesas Technology Corp

부품명 RX72N
상세설명  Renesas MCUs
PDF  179 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RX72N 데이터시트(HTML) 5 Page - Renesas Technology Corp

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RX72N Group
1. Overview
R01DS0343EJ0120 Rev.1.20
Page 5 of 179
Nov 15, 2023
DMA
DMA controller
(DMACAa)
 8 channels
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software trigger and interrupt requests from peripheral functions
EXDMA controller
(EXDMACa)
 2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster
transfer
 Single-address transfer enabled with the EDACKn signal
 Request sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Data transfer controller
(DTCb)
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Request sources: External interrupts and interrupt requests from peripheral functions
 Sequence transfer
I/O ports
Programmable I/O ports
 I/O ports for the 224-pin LFBGA
I/O pins: 182
Input pin: 1
Pull-up resistors: 182
Open-drain outputs: 182
5-V tolerance: 19
 I/O ports for the 176-pin LFBGA and 176-pin LFQFP
I/O pins: 136
Input pin: 1
Pull-up resistors: 136
Open-drain outputs: 136
5-V tolerance: 19
 I/O ports for the 145-pin TFLGA and 144-pin LFQFP
I/O pins: 111
Input pin: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 18
 I/O ports for the 100-pin LFQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 17
Event link controller (ELC)
 Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
 135 internal event signals can be freely combined for interlinked operation with
connected functions.
 Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Table 1.1
Outline of Specifications (4/11)
Classification
Module/Function
Description



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