RZSLASHG2UL datasheet(33/67 Pages) RENESAS

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RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 33 of 67

Jun 16, 2025

3.5.4

LCDC Access Timing

Table 3.27

LCDC AC Access Timing

Item

Symbol

Min.

Max.

Unit

Figures

DCLK period

tLcyc

11.5

172.33

Figure 3.11

DCLK low pulse width

tLOL

tLcyc/2 − 1.06

tLcyc/2 + 1.06

DCLK high pulse width

tLOH

tLcyc/2 − 1.06

tLcyc/2 + 1.06

DCLK rise time

tLOR

—

DCLK fall time

tLOF

—

Data output dealy

tDD

−1.5

1.5

Note: AC access timing condition: SR = 1 (fast) / Drive capacity setting 12 mA / Load capacity 30 pF.

DISP_CLK

DISP_VSYNC

DISP_HSYNC

DISP_DE

DISP_DATA[23:0]

DISP_VSYNC

DISP_HSYNC

DISP_DE

DISP_DATA[23:0]

Case-1)

Case-2)

70%

30%

70%

30%

70%

30%

tLcyc

tLOH

tLOL

tDD

tLOF

tLOR

Note: Case-1) DISP_CLK forward rotation output mode

When DPI_CLKMD bit in DU_DITR0 register is 0.

Case-2) DISP_CLK inverted output mode

When DPI_CLKMD bit in DU_DITR0 register is 1.

Figure 3.11

LCDC AC Access Timing

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