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MK50H25 데이터시트(PDF) 55 Page - STMicroelectronics

부품명 MK50H25
상세설명  HIGH SPEED LINK LEVEL CONTROLLER
PDF  64 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MK50H25 데이터시트(HTML) 55 Page - STMicroelectronics

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A 16-23
ALE
SYSCLK
BM0,1
READY
DAS
HLDA
HOLD
25
65
26
27
40
23
23
43
44
41
42
28
22
60
61
48
48
T1
T2
T3
T4
T5
DATA
ADDR
DAL0-15
READ
DALO
DALI
29
34
33
35
45
ADDRESS
64
24
NOTES:
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
until the slave device returns READY.
1. This Reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE = 1.
Times T0 and T5 from the standard DMA Cycle are removed for this reduced timing.
Figure 8a: MK50H25 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>)
MK50H25
55/64



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