ICS557-03

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE

PCIE SSCG

IDT®

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE

8

ICS557-03

REV U 112111

AC Electrical Characteristics - CLKOUT, LVDS

Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85

° C

1 Test setup is R

L=50 ohms with 2 pF, Rr = 475Ω (1%).

2 Measurement taken from a single-ended waveform.

3 Measurement taken from a differential waveform.

4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.

5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.

Electrical Characteristics - Differential Phase Jitter

Note 1: Guaranteed by design and characterization, not 100% tested in production.

Note 2: See http://www.pcisig.com for complete specs.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

25

MHz

Output Frequency

LVDS termination

100

MHz

Differential Output Voltage

VOD

247

454

mV

Offset Voltage

VOS

1.125

1.375

V

∆V

OD

|Change to V

OD|

50

mV

∆V

OS

|Change to V

OS|

50

mV

Jitter, Cycle-to-Cycle1,3

80

ps

Modulation Frequency

Spread spectrum

30

31.5

33

kHz

Slew Rate, Rise1,3

tSLR

Measured from ±150 mV from

crossing point voltage

14

V/ns

Slew Rate, Fall1,3

tSLF

Measured from ±150 mV from

crossing point voltage

14

V/ns

Skew between outputs

At crossing point Voltage

50

ps

Duty Cycle1,3

45

55

%

Output Enable Time5

All outputs

12

µs

Output Disable Time5

All outputs

12

µs

Power-up Time

tSTABLE

From power-up VDD=3.3 V

3

3.5

ms

Spread Change Time

tSPREAD Settling period after spread change

3

3.5

ms

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

Jitter, Phase

tjphasePLL

PCIe Gen 1

-

-

86

ps (p-p)

1, 2