ICS557-03

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE

PCIE SSCG

IDT®

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE

2

ICS557-03

REV U 112111

Pin Assignment

Output Select Table 1 (MHz)

Spread Selection Table 2

Pin Descriptions

1

2

3

X2

4

S1

5

6

CLK0

7

8

CLK0

GNDODA

VDDXD

OE

SS0

16

X1/ICLK

SS1

CLK1

VDDODA

15

14

13

12

11

10

9

16-pin (173 mil) TSSOP

GNDXD

S0

IREF

CLK1

S1

S0

CLK(1:0), CLK(1:0)

00

25M

0

1

100M

1

0

125M

1

1

200M

SS1

SS0

Spread%

00

No Spread

0

1

Down -0.5

1

0

Down -0.75

11

No Spread

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

S0

Input

Select pin 0. See Table1. Internal pull-up resistor.

2

S1

Input

Select pin 1. See Table 1. Internal pull-up resistor.

3

SS0

Input

Spread Select pin 0. See Table 2. Internal pull-up resistor.

4

X1/ICLK

Input

Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.

5

X2

Output

Crystal connection. Leave unconnected for clock input.

6

OE

Input

Output enable. Tri-states outputs and device is not shut down. Internal

pull-up resistor.

7

GNDXD

Power

Connect to ground.

8

SS1

Input

Spread Select pin 1. See Table 2. Internal pull-up resistor.

9

IREF

Output

Precision resistor attached to this pin is connected to the internal current

reference.

10

CLK1

Output

HCSL complimentary clock output 1.

11

CLK1

Output

HCSL true clock output 1.

12

VDDODA

Power

Connect to voltage supply +3.3 V for output driver and analog circuits

13

GNDODA

Power

Connect to ground.

14

CLK0

Output

HCSL complimentary clock output 0.

15

CLK0

Output

HCSL true clock output 0.

16

VDDXD

Power

Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.