WM8951L datasheet(22/42 Pages) WOLFSON

22 / 42 page

WM8951L

Production Data

PD Rev 4.1 December 2007

The digital audio interface takes the data from the internal ADC digital filter and places it on the

ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital

filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls

whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are

synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low

transition. BCLK maybe an input or an output dependent on whether the device is in master or slave

mode. Refer to the MASTER/SLAVE OPERATION section

There are four digital audio interface formats accommodated by the WM8951L. These are shown in

the figures below. Refer to the Electrical Characteristic section for timing information.

Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR

transition.

Figure 17 Left Justified Mode

2S mode is where the MSB is available on the 2nd rising edge of BCLK following an ADCLRC

transition.

Figure 18 I2S Mode

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a ADCLRC

transition, yet MSB is still transmitted first.

WM8951L 데이터시트(PDF) 22 Page - Wolfson Microelectronics plc