STA323WQS datasheet(17/78 Pages) STMICROELECTRONICS

17 / 78 page

STA323WQS

Pin out

17/78

CLK (pin 27)

This is the master clock input used by the digital core. The master clock must be an integer

multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz

(256 * fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken

to provide the device with the nominal system clock frequency; over-clocking the device may

result in anomalous operation, such as inability to communicate.

PLL_FILTER (pin 26)

This is the connection for the external filter components for the PLL loop compensation.

Refer to the schematic diagram Figure 9: Power schematic for 1 mono parallel channel on

page 14 for the recommended circuit.

BICKI (pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically

64 * fs using I2S serial format.

SDI (pin 30)

This is the serial data input where PCM audio information enters the device. Six format

choices are available including I2S, left or right justified, LSB or MSB first, with word widths

of 16, 18, 20 and 24 bits.

LRCKI (pin 31)

The left/right clock input is for data word framing. The clock frequency is at the input sample

rate, fs.

STA323WQS 데이터시트(PDF) 17 Page - STMicroelectronics