STA323WQS datasheet(49/78 Pages) STMICROELECTRONICS

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STA323WQS

49/78

Setting the IDE bit enables this function, which looks at the input I2S data and clocking and

automatically mutes all outputs if the signals are invalid.

Detects loss of input MCLK in binary mode and outputs 50% duty cycle to prevent audible

noise when input clocking is lost.

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss

detection.

EAPD is used to actively power down a connected DDX® power device. This register has to

be written to 1 at start-up to enable the DDX® power device for normal operation.

Table 44.

Output configuration selections

OCFG[1:0]

Output power configuration

2 channel (full-bridge) power, 1 channel DDX:

1A/1B

◊ 1A/1B

2A/2B

◊ 2A/2B

2(half-bridge).1(full-bridge) on-board power:

◊ 1A

Binary

◊ 1B

Binary

3A/3B

◊ 2A/2B Binary

Reserved

1 channel mono-parallel:

◊ 1A/1B

◊ 2A/2B

Table 45.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

2RW

IDE

0: disabled

1: enabled

Table 46.

Binary clock loss detection enable

Bit

R/W

RST

Name

Description

5RW

BCLE

0: disabled

1: enabled

Table 47.

Auto-EAPD on clock loss enable

Bit

R/W

RST

Name

Description

7RW

ECLE

0: disabled

1: enabled

Table 48.

External amplifier power down

Bit

R/W

RST

Name

Description

EAPD

0: external power stage power down active

1: normal operation

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