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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADSP-CM403CSWZ-CF 데이터시트(PDF) 87 Page - Analog Devices |
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ADSP-CM403CSWZ-CF 데이터시트(HTML) 87 Page - Analog Devices |
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87 / 124 page  Rev. A | Page 87 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPT_TDV is asserted for communication with external devices. Table 45. Serial Ports—Transmit Data Valid (TDV) Parameter Min Max Unit Switching Characteristics tDRDVEN Data-Valid Enable Delay from Drive Edge of External Clock1 1 Referenced to drive edge. 2ns tDFDVEN Data-Valid Disable Delay from Drive Edge of External Clock 1 14 ns tDRDVIN Data-Valid Enable Delay from Drive Edge of Internal Clock 1 –1 ns tDFDVIN Data-Valid Disable Delay from Drive Edge of Internal Clock 1 3.5 ns Figure 33. Serial Ports—Transmit Data Valid Internal and External Clock DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK EXTERNAL) tDRDVEN tDFDVEN DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK INTERNAL) tDRDVIN tDFDVIN SPT_A/BTDV SPT_A/BTDV |
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