74LVC74A

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 7 — 20 November 2012

9 of 19

NXP Semiconductors

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

11. AC waveforms

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7.

The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,

the nCP to nD hold times, and the maximum frequency

mna422

th

tsu

th

tPHL

tPHL

tW

tPLH

tPLH

tsu

1/fmax

VM

VM

VM

VM

VI

GND

VI

GND

nCP input

nD input

VOH

VOL

nQ output

VOH

VOL

nQ output