74LVC74A

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 7 — 20 November 2012

10 of 19

NXP Semiconductors

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8.

The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse

widths, and the nRD to nCP recovery time

mna423

trec

tPHL

tPHL

tW

tPLH

tPLH

VM

VM

VM

tW

VM

VM

VI

GND

VI

GND

nSD input

VI

GND

nRD input

nCP input

VOH

VOL

nQ output

VOH

VOL

nQ output

Table 9.

Measurement points

Supply voltage

Input

Output

VCC

VI

VM

VM

1.2 V

VCC

0.5

 V

CC

0.5

 V

CC

1.65 V to 1.95 V

VCC

0.5

 V

CC

0.5

 V

CC

2.3 V to 2.7 V

VCC

0.5

 V

CC

0.5

 V

CC

2.7 V

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

2.7 V

1.5 V

1.5 V