NRF52811-QCAA-R datasheet(38/444 Pages) NORDIC

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Core components

• If two (or more) bus masters request access to the same slave device, the master with the highest

priority is granted the access first.

• Bus masters with lower priority are stalled until the higher priority master has completed its

transaction.

• If the higher priority master pauses at any point during its transaction, the lower priority master in

queue is temporarily granted access to the slave device until the higher priority master resumes its

activity.

• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.

Below is a list of bus masters in the system and their priorities.

Bus master name

Description

CPU

SPIM0/SPIS0

Same priority and mutually exclusive

RADIO

CCM/ECB/AAR

Same priority and mutually exclusive

SAADC

UARTE0

TWIM0/TWIS0

Same priority and mutually exclusive

PDM

PWM

Table 11: AHB bus masters (listed in priority order, highest to lowest)

Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available

slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection

matrix is illustrated in Memory on page 16.

4.8 Debug

Debug system offers a flexible and powerful mechanism for non-intrusive debugging.

DAP

CPU

ARM Cortex-M4

SWDCLK

SWDIO

SW-DP

POWER

CxxxPWRUPREQ

CxxxPWRUPRACK

Power

External

debugger

Peripherals

RAM & flash

APB/AHB

AHB

AHB-AP

DAP bus

interconnect

APPROTECT.PALL

CTRL-AP

UICR

NVMC

Figure 7: Overview

The main features of the debug system are:

• Two-pin serial wire debug (SWD) interface

• Flash patch and breakpoint (FPB) unit supports:

4454_140 v1.0

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