CS495303 datasheet(36/38 Pages) CIRRUS

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CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

DS705PP2

10. Revision History

Revision

Date

Changes

FEB 2006

Advance release.

JUN 2006

Updated part numbers for ordering (Tables 5 & 6), Updated VOH and VOL specification to

include the current load used for testing

JUL 2006

Updated part numbers for ordering (Tables 5 &6). Updated text in sections 3 and 4.

Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and

Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS#. Added footnote to

XTI table. Removed SCLK/LRCLK relative timing from DAI port timing. Removed

SCLK/LRCLK slave relative timing from DAO port timing.

OCT 2007

Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This

applies to both SPI ports.

PP1

May 28, 2008

Updated product feature list in Table 2. Updated Figure 21 and Figure 22.

PP2

June 20, 2008

Added typical crystal frequency values in Table Footnote 1 and Max and Min values of

Fxtalin Section 5.8. Removed DSD Phase Modulation Mode from Section 5.18.

Removed reference to MCLK in Section 5.18. Redefined Master mode clock

speed for SCP_CLK in Section 5.11.. Redefined DC leakage characterization

data in Section 5.3, correcting units of measurement. Modified Footnote 1 under

Section 5.10

CS495303 데이터시트(PDF) 36 Page - Cirrus Logic