ST10F280-JT3 datasheet(78/186 Pages) STMICROELECTRONICS

78 / 186 page

ST10F280

78/186

When an external bus mode is enabled, the direc-

tion of the port pin and the loading of data into the

port output latch are controlled by the bus control-

ler hardware.

The input of the port output latch is disconnected

from the internal bus and is switched to the line

labeled “Alternate Data Output” via a multiplexer.

The alternate data can be the 16-bit intra-segment

address or the 8/16-bit data information. The

incoming data on PORT0 is read on the line

“Alternate Data Input”. While an external bus

mode is enabled, the user software should not

write to the port output latch, otherwise unpredict-

able results may occur. When the external bus

modes are disabled, the contents of the direction

The Figure 30 shows the structure of a PORT0

pin.

Figure 30 : Block Diagram of a PORT0 Pin

Direction

Latch

Write DP0H.y / DP0L.y

Read DP0H.y / DP0L.y

Port Output

Latch

Write P0H.y / P0L.y

Read P0H.y / P0L.y

MUX

Alternate

Data

Output

MUX

Alternate

Direction

Input

Latch

P0H.y

P0L.y

Output

Buffer

y = 7...0

Alternate

Function

Enable

Port Data

Output

CPU Clock

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