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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST10F280-JT3 데이터시트(PDF) 47 Page - STMicroelectronics |
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ST10F280-JT3 데이터시트(HTML) 47 Page - STMicroelectronics |
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47 / 186 page  ST10F280 47/186 Figure 11 : Chip Select Delay 7.2 - READY Programmable Polarity The active level of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx reg- isters. When the READY function is enabled for a specific address window, each bus cycle within this win- dow must be terminated with the active level defined by this RDYPOL bit in the associted BUSCON register. BUSCON0 (FF0Ch / 86h) SFR Reset Value: 0xx0h BUSCON1 (FF14h / 8Ah) SFR Reset Value: 0000h BUSCON2 (FF16h / 8Bh) SFR Reset Value: 0000h 15 14 13 12 11 10 9876543210 CSW EN0 CSRE N0 RDY POL0 RDY EN0 - BUS ACT0 ALE CTL0 - BTYP MTT C0 RWD C0 MCTC RW RW RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9876543210 CSW EN1 CSR EN1 RDY POL1 RDY EN1 - BUS ACT1 ALE CTL1 - BTYP MTT C1 RWD C1 MCTC RW RW RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9876543210 CSW EN2 CSR EN2 RDY POL2 RDY EN2 - BUS ACT2 ALE CTL2 - BTYP MTT C2 RWD C2 MCTC RW RW RW RW RW RW RW RW RW RW Normal CSx RD Address (P1) ALE Segment (P4) Normal Demultiplexed Bus Cycle ALE Lengthen Demultiplexed Bus Cycle Unlatched CSx WR Read/Write Delay Data Data Data Data BUS (P0) BUS (P0) Read/Write Delay |
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